1. Field of the Invention
The present invention relates to the field of memories, and more particularly, to a memory and a related method capable of decreasing power consumption and enhancing accessing efficiency.
2. Description of the Prior Art
In modern information society, documents and data are transmitted, managed, and stored in the form of electronic signals, for this reason, memory device and memory circuits capable of accessing data are widely used in various fields. For example, in the field of communication, read-only memories, which store data in a non-volatile manner, generally are disposed in communication chips of cell phones for storing codes utilized for processing signals or other necessary parameters and vectors.
As known by those skilled in the art, a plurality of memory units, each utilized for storing one bit of data, is disposed in a memory. The memory units are arranged in array having a plurality of row lines and a plurality of column lines intersecting respectively. Each memory unit represents one bit of data according to various circuit structures thereof. For example, a memory unit storing “1” has no transistor whereas a memory unit storing “0” has a transistor. Generally, one of the drain/source of the transistor is connected to a column line, another is grounded with a low voltage level, and the gate is connected to the row line.
A memory unit has a pre-charge circuit and a holding circuit for pre-charging the column line and maintaining the voltage level of the column line when accessing an objective memory unit.
When accessing an objective memory unit of a given column line, all of the column lines of the memory array are pre-charged to a high voltage level (for example, a positive bias voltage VDD) and the holding circuit is activated for maintaining the high voltage level of the column lines. The pre-charging is then stopped to enable the objective memory unit, as a result, the voltage level of the given column of the objective memory unit is changed according to the stored data. If the objective memory unit has no transistors and stores a digital bit “1”, the high voltage level of the given column line (or bit line) is maintained by the holding circuit. If the objective memory unit has a transistor and stores a digital bit “0”, the transistor is turned on to discharge the column line to a ground voltage. According to the voltage level of the given column line, a sense amplifier reads out the data stored in the objective memory unit. An accessing cycle (or a reading cycle) is thus regarded as from the pre-charging to the data reading.
However, the conventional memory has some disadvantages. When accessing an objective memory unit, the conventional memory has to pre-charge all of the column lines, so that a great power is consumed. Otherwise, if the objective memory unit has a transistor, the holding circuit will fight against the transistor of the objective memory unit. As mentioned above, in order to correctly read out the data, the memory units having transistors need to discharge the column lines through conduction transistors. However, since the column lines have been pre-charged to the high voltage level, the transistors of memory units pull down the voltage level of the column lines to ground after certain time of conduction. Unfortunately, for maintaining the voltage level of the column line, the holding circuit must fight against the discharging of the memory unit, and thus, the memory unit spends much more time on discharging. In other words, the accessing cycle of the conventional memory is relatively long, which results in a low accessing efficiency.